Stock Markets June 25, 2026 06:09 AM

IBM Announces Breakthrough 0.7nm Chip Technology, Targets AI Compute Density Gains

Company says new 'nanostack' transistor architecture packs nearly 100 billion transistors on a fingernail-size surface and could enter production within five years

By Nina Shah
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IBM revealed a transistor architecture measuring 0.7 nanometers that it says is the first technology capable of producing chips smaller than one nanometer. The design, called 'nanostack', stacks transistors vertically to increase density and claims nearly double the transistor packing of IBM’s prior 2-nanometer design, offering higher performance or improved energy efficiency. IBM says production could begin within five years and has not named a manufacturing partner.

IBM Announces Breakthrough 0.7nm Chip Technology, Targets AI Compute Density Gains
IBM
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Key Points

  • IBM introduced a 0.7-nanometer transistor architecture called "nanostack" that stacks transistors vertically to increase density and efficiency - impacts semiconductor and AI computing sectors.
  • Company claims the new design places nearly 100 billion transistors on a fingernail-sized surface, about double the density of its 2-nanometer chip, promising up to 50% higher performance or 70% greater energy efficiency - relevant to hardware manufacturers and data center operators.
  • IBM says production could begin within five years but has not announced a manufacturing partner; the development changes competitive dynamics among contract chipmakers such as TSMC and Intel and could affect capital spending in the foundry sector.

IBM on Thursday unveiled what it described as the first technology able to produce semiconductor chips smaller than one nanometer, positioning the company to pursue denser, more energy-efficient processors tailored to demanding AI workloads.

The Armonk, New York-based firm described a transistor architecture of 0.7 nanometers, or 7 angstroms, built around a new approach to device geometry it calls "nanostack." Instead of placing transistors side-by-side on a single plane, the nanostack concept stacks transistor elements in three dimensions. IBM said this vertical stacking lets designers fit substantially more switching elements into the same physical volume.

According to IBM, the 0.7-nanometer chip integrates nearly 100 billion transistors on a surface no larger than a fingernail. The company said this represents roughly twice the transistor density of the 2-nanometer chip it introduced in 2021 and yields either up to 50% higher performance or up to 70% greater energy efficiency, depending on design trade-offs.

"With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency," Jay Gambetta, director of IBM Research, said in the company announcement.

The disclosure arrives as chipmakers aim to continue the long-standing industry trend of increasing transistor counts in smaller areas - Moore’s Law - to meet expanding compute demands driven in part by AI. IBM framed the nanostack advance as strengthening its competitive stance against major contract manufacturers, naming TSMC and Intel as industry rivals.

Intel last week said its next-generation 18A process, which it described as making 1.8-nanometer-class chips, had moved into risk production, the testing phase before commercial manufacturing. IBM did not announce a foundry partnership for the 0.7-nanometer technology; the company has previously licensed other chip technologies to Samsung and Japan’s Rapidus.

On the market, IBM shares rose more than 6% in premarket trading following the announcement. The stock, IBM said, has declined about 11% so far this year. IBM also stated that production of the 0.7-nanometer technology could begin within five years.


The information provided reflects IBM’s statements about the new transistor architecture, performance and timeline. No manufacturing partner for this specific technology has been named.

Risks

  • No manufacturing partner has been announced for the 0.7-nanometer technology, creating uncertainty about commercialization and timelines - this is a risk for the semiconductor manufacturing and foundry sectors.
  • IBM’s production timeline of up to five years leaves execution risk and potential delays before chips reach commercial markets - affecting AI hardware suppliers and enterprise buyers relying on future supply.
  • Competitive progress by other chipmakers, including Intel’s move of its 18A process into risk production for 1.8-nanometer chips, poses market and technological competition risk - impacting market positioning for contract manufacturers and CPU/GPU vendors.

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