Stock Markets February 26, 2026

ASML Says High-NA EUV Tools Are Ready for Volume Production, Clearing a Path for AI Chip Scaling

Company cites machine uptime, imaging precision and half-a-million wafer runs as evidence that next-generation lithography can replace multiple legacy steps

By Caleb Monroe ASML TSM INTC
ASML Says High-NA EUV Tools Are Ready for Volume Production, Clearing a Path for AI Chip Scaling
ASML TSM INTC

ASML's newest High-NA extreme ultraviolet (EUV) lithography systems have reached technical readiness for mass production, the company's chief technology officer said, based on uptime progress, imaging precision and processing of 500,000 wafers. The machines, which cost roughly $400 million each, aim to let chipmakers consolidate multiple manufacturing steps into a single High-NA operation, though broad factory integration will require two to three years of customer testing and qualification.

Key Points

  • ASML’s High-NA EUV machines have processed about 500,000 wafers and show imaging precision sufficient for advanced chip circuit patterns.
  • The next-generation tools cost about $400 million each - roughly double the price of the original EUV systems - and currently achieve roughly 80% uptime with a plan to reach 90% by year-end.
  • Broad factory integration will still require two to three years of testing and qualification by chipmakers such as Taiwan Semiconductor Manufacturing and Intel.

SAN JOSE, California, Feb 26 - ASML Holding has reached a milestone with its next-generation lithography equipment, its chief technology officer said on Wednesday, arguing the machines are prepared for deployment in high-volume chip production. The Dutch firm builds the only commercially available extreme ultraviolet (EUV) lithography tools used by advanced chipmakers, and its latest systems - High-NA EUV tools - are positioned to remove several costly and complex steps from the semiconductor production flow.

According to Marco Pieters, ASML’s chief technology officer, three performance indicators together support the claim that the High-NA systems are ready for manufacturers to begin incorporating them at scale: substantially improved uptime, imaging resolution adequate to draw the critical chip circuit patterns, and the machines' ability to process a large number of wafers without major interruptions. Pieters said the tools have now processed about 500,000 dinner-plate-sized silicon wafers and are experiencing limited downtime, while producing images that meet the precision required for modern circuit layouts.

The company intends to publish the underlying imaging data at a technical conference in San Jose on Thursday, citing it as a key milestone for the new tools. Pieters said the combination of the three data elements - uptime, throughput of wafers, and imaging capability - provides sufficient evidence for customers to consider replacing multiple steps performed with older-generation equipment with a single High-NA step.

Developing these next-generation machines has been a multi-year, capital-intensive effort. The High-NA EUV tools command a price roughly double that of the original EUV generation, coming in at about $400 million per unit. That expense has weighed on the calculus for chip manufacturers as they evaluate when it becomes economically sensible to transition from current equipment to the new systems.

Pieters acknowledged that although the hardware has reached technical readiness, broad integration into production lines will not be immediate. He estimated that chipmakers will need two to three years of testing and development to qualify and fully integrate the High-NA systems into their manufacturing operations. "I think that it’s at a critical point to look at the amount of learning cycles that have happened," he said, referring to the number of tests and customer trials conducted on the machines.

ASML reported current uptime for the High-NA systems at roughly 80 percent, with a target of reaching 90 percent by the end of the year. The 500,000 wafers processed to date have provided the company with opportunities to identify and correct many early issues, Pieters said, contributing to improved reliability and performance.

The company highlighted the implications for chipmakers including Taiwan Semiconductor Manufacturing and Intel, saying the High-NA tools can enable those manufacturers to produce more powerful and efficient chips. In particular, ASML noted that the higher-resolution capabilities are important as existing EUV systems approach the limits of their ability to pattern the most complex designs used in advanced AI chips - a constraint that has made the industry closely watch the maturation of High-NA equipment.

While the tools are being presented as technically fit for mass production, Pieters emphasized that individual manufacturers must complete their own qualification processes. "(Chipmakers) have all the knowledge to qualify these tools," he said, underlining that customer validation and factory integration remain necessary steps before High-NA systems can be broadly adopted in production environments.


Context and implications

The readiness of High-NA EUV systems represents a technical turning point for the semiconductor supply chain, with potential downstream effects on the manufacturing of advanced logic and AI-optimized chips. Even with demonstrated machine readiness, the transition timeline is driven by customer validation cycles and factory readiness, which ASML places at two to three years for widespread integration.

Risks

  • High cost per unit - each High-NA EUV tool costs approximately $400 million, potentially delaying purchase decisions by chip manufacturers; impacts capital-intensive semiconductor equipment spending and chipmakers' capital allocation.
  • Integration timeline uncertainty - despite technical readiness, ASML says it will take two to three years for customers to qualify and integrate the tools, posing timing risk for chip production roadmaps in the semiconductor sector.
  • Operational reliability targets - current uptime is around 80% with a target of 90% by year-end; failure to reach reliability goals could slow adoption and affect production planning for advanced chip manufacturers.

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