Taiwan Semiconductor Manufacturing Co unveiled on Wednesday a pair of process and packaging advances that the company says will enable smaller, faster chips while making continued use of its existing extreme-ultraviolet (EUV) lithography fleet rather than switching to a newer, pricier generation of lithography tools.
TSMC described two technology tracks. The first, labeled A13, is targeted for production in 2029 and is positioned as a likely fit for artificial intelligence accelerators. The second, called N2U, is presented as a more cost-conscious variant suitable for smartphones, laptops and some AI workloads.
Across the technologies shown, TSMC emphasized that it plans to extract additional performance and density gains from its current EUV machines supplied by ASML rather than moving to the so-called high-NA EUV systems. Those higher-NA machines come at roughly double the capital cost of the existing generation - about $400 million apiece - a consideration TSMC highlighted as it outlined its roadmap.
Kevin Zhang, deputy co-chief operations officer and senior vice president at TSMC, said: "This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap. This is definitely a strength."
Even with the improvements, TSMC indicated that incremental gains from shrinking and speeding transistors will be modest. The company concurrently showcased an expanded approach to multi-die integration - known as stitching - that executives and industry observers see as the route to larger performance improvements for AI processors.
Current large AI chips produced by TSMC, such as the forthcoming Vera Rubin design for Nvidia, combine two large compute dies with eight stacks of high-bandwidth memory. TSMC said that by 2028 it expects to be able to stitch together packages containing up to 10 large compute dies and 20 stacks of high-bandwidth memory, which would substantially increase on-package compute and memory capacity.
Observers framed the multi-die approach as a continuation of the historical drive toward higher compute density, commonly associated with Moore's law. Dan Hutcheson, vice chair of TechInsights, said: "Moore’s law is morphing from a monolithic, single die in a package to multi-die in a package. And that allows the power and performance gains."
The multi-die packaging strategy introduces its own engineering hurdles. When multiple dies and memory stacks operate within a single large package, thermal loads increase and differing materials used for packaging expand at different rates. Those mismatches can create mechanical stress, raising the risk of bending or cracking in large packages.
Ian Cutress, chief analyst at consultancy More Than Moore, noted that large-package reliability has been an issue, citing problems reported on previous Nvidia designs. He added: "(TSMC) aren’t addressing directly how they are solving those challenges."
TSMC presented its pathway as a balance between incremental transistor-level improvements via refined EUV usage and larger system-level gains through multi-die stitching. The company is positioning A13 for AI chipmaking and N2U as a more affordable node for client devices while planning to increase the scale of stitched packages over the next few years.
What this means
- TSMC plans to squeeze more performance from its installed EUV tools rather than adopt high-NA EUV machines that cost roughly twice as much.
- A13 is scheduled for 2029 and is aimed at AI accelerators; N2U is a lower-cost variant for phones, laptops and some AI uses.
- Stitching will expand the number of compute dies and memory stacks per package - TSMC projects potential assemblies of 10 compute dies and 20 memory stacks by 2028.
The company’s roadmap ties transistor scaling advances to packaging innovations, with the latter expected to deliver the largest near-term jumps in on-package compute density for AI workloads.